This invention relates to an improvement in microprocessor architecture and more particularly to a single chip microprocessor central processing unit (CPU) in which the control signals from the instruction decoder may be directly observed at the terminals of the chip during testing.
Microprocessor CPUs which are fabricated on a single integrated circuit chip are known in the art. Such CPU chips are designed to execute a program of instructions and typically include a plurality of input terminals, a plurality of output terminals, instruction decoding means for receiving at least a portion of an instruction during an instruction cycle and for controlling the performance of one or more processor operations specified by the instruction, the instruction decoding means having a multiplicity of control lines for providing during the instruction cycle control signals corresponding to the one or more processor operations specified by the instruction. The input and output terminals may be bonding pads on the chip or package pins in the case of a packaged chip. The instruction decoding means may be a programmable logic array (PLA) or a microprogrammed random logic controller.
One problem with the prior art microprocessor CPU is the difficulty in performing functional tests on the CPU chip. Unlike the case of a CPU in a minicomputer or a mainframe computer, the functional parts of a single chip CPU such as the instruction decoder cannot be separately tested. This is because the internal nodes of an integrated circuit chip are not, as a practical matter, accessible for testing. Functional tests on single chip CPUs are generally performed by applying a sequence of binary logic level patterns called test vectors to the input terminals of the chip and by observing the sequence of binary logic level patterns called output patterns appearing at the output terminals of the chip in response to the applied test vectors. The observed output patterns are compared with the "correct" output patterns as would be expected from a functioning chip. If an output pattern from a chip under test is found to disagree with the "correct" output pattern, the chip has one or more logical faults in one or more of its functional parts. Functional testing which is used to detect logical faults in an integrated circuit is an important step in the manufacturing process for the chip. The sequence of test vectors is normally applied to the chip by automatic testing equipment.
In addition to detecting faulty chips, functional testing may also provide information concerning the identification of those functional parts having logical faults as well as the nature of the logical faults. Such information is useful for diagnosing design problems in a newly designed CPU chip. A sequence of test vectors which is to be used for diagnostics is normally designed, not only to produce specific output patterns as a result of logical faults in the CPU chip but also to permit the unambiguous identification of logical faults when an output pattern indicating a fault is detected.
However, owing to the complexity of a CPU chip and the fact that its functional parts are not testable separately but only collectively as parts of a particular signal path between input and output terminals, not all logical faults which may potentially exist in the chip can be detected and not all detected logical faults can be unambiguously identified. Generally, a sequence of test vectors used for manufacture is designed to maximize the number of potential logical faults which can be detected with the sequence, whereas a diagnostic test vector sequence is designed to maximize the number of potential logical faults which can be both detected and identified with the sequence. A figure of merit for a sequence of test vectors is the percentage of all potential logical faults in the chip which are detectable with the sequence. This figure of merit is commonly referred to as the fault coverage of the sequence. For reasons discussed above it is generally not possible to achieve a 100 percent fault coverage in the functional testing of a prior art CPU chip. A CPU chip having an undetectable logical fault would pass final testing as good product, and only later be identified as a failed device during actual operation in the field. Consequently, logical faults in chips which are not detected during functional testing can make the entire chip unreliable.
I have discovered that most of the undetectable and unidentifiable potential logical faults in a prior art CPU exist in the instruction decoder which generates the control signals governing all processor operations. These control signals, which are distributed to virtually all other functional parts of the CPU, are not directly accessible for testing but may only be indirectly observed through the operation of the other functional parts which they control. Therefore, even though a logical fault in the instruction decoder causes an error in a control signal, the erroneous control signal may not always give rise to an erroneous output pattern. For example, the erroneous control signal may, in a particular test, only affect a functional part which is not in the signal path of the output pattern, or another logical fault in the signal path may give rise to a compensating error in the output pattern. In some cases, by adding more test vectors to the test program, the control signal error can be made to propagate to the output terminals, but not all potential logical faults in the instruction decoder of a prior art CPU chip can be made detectable by presently known techniques. In general, a long test program is necessary to achieve a relatively high fault coverage in the functional testing of a prior art CPU chip. In an example of a prior art CPU chip, a fault coverage of 95% is achieved with a test program having 25,000 test vectors. However, a long test program leads to a high testing cost. As CPU chips of greater complexity are designed in accordance with the prior art, the problem of a long test program becomes more serious as the testing cost may become a major part of the cost of manufacturing a microprocessor chip.
Therefore, a need clearly exists for an improved CPU architecture which would increase microprocessor chip reliability by improving the functional test fault coverage of the chip and/or which would reduce functional testing cost by permitting shorter test programs.